A traditional dense library is illustrated in FIG. 1A. The layout includes metal 1 (M1) layer portions 101, 103, and 105, power rails 107 (which are also part of the M1 layer), vias (V0) 109, gate contacts 111, gate lines 113, active areas 115 and 117 for a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), respectively, and source/drain contacts (CA's) 119. The M1 layer is shown separately in FIG. 1B, portion 121 showing a 2-CPP cross-coupling is shown in FIG. 1C, and the source/drain contact pattern is shown separately in FIG. 1D. As illustrated, M1 requires 3 color patterning, as indicated by segments 101, 103, and 105 and is bidirectional and zigzag. In addition, for the cross-coupling, the CA pattern includes an irregular, diagonal shape, which prevents use of self-aligned double patterning (SADP) for patterning the source/drain contacts.
A need therefore exists for methodology enabling formation of a unidirectional M1 layer with SADP friendly cross-coupling and the resulting device.